(1) Field of the Invention
The present invention relates to a semiconductor storage apparatus.
(2) Description of the Related Art
Some semiconductor storage apparatuses use a ferroelectric memory. The ferroelectric memory is a nonvolatile memory using the remnant polarization of a ferroelectric film as a data storage means (see U.S. Pat. No. 4,873,664). It is known that the life of the ferroelectric memory is closely related to the number of times data is read out. As a technology for extending the life of a semiconductor storage apparatus using a ferroelectric memory, there has been proposed a semiconductor storage apparatus using a cache memory and a ferroelectric memory (for example, Japanese Patent Application Publication No. 6-215589). In this semiconductor storage apparatus, data stored in the ferroelectric memory is partly copied into the cache memory. And data is read out mainly from the cache memory, and only if a desired piece of data is not stored in the cache memory (only if a cache mishit occurs), the desired piece of data is read out from the ferroelectric memory. With this construction, the number of times data is read from the ferroelectric memory is reduced, resulting in the extension of the life of the semiconductor storage apparatus.
Meanwhile, there is one design item to be determined when a cache memory is incorporated into a semiconductor storage apparatus. That is a replacement algorithm. The replacement algorithm is used to determine which existent block of data should be replaced with a new block of data when the cache memory does not have enough space to store the new block of data. The afore-said Japanese Patent Application Publication No. 6-215589 discloses the incorporation of the cache memory, but not the replacement algorithm. Typically used replacement algorithms include LRU (Least Recently Used) and NRU (Not Recently Used) This LRU selects a least recently used block of data, as the block of data to be replaced with a new block of data. The NRU selects a block of data that has not been used recently, as the block of data to be replaced with a new block of data.
However, a problem in achieving such a replacement algorithm is that it is necessary to manage the use state of data stored in the cache memory, which makes the hardware construction complex. For example, in the case of LRU, a need arises to provide a hardware component that arranges blocks of data in the order of the accesses, and rearranges the blocks of data each time data is accessed. Also, in the case of NRU, it is required to have a hardware component that manages the accesses for each block of data, and updates the management information each time data is accessed.